D3.5: Hardware Vulnerability and Leakage Detection (first version)

In this deliverable we summarize the activities of Task 3.3 till M14 of the RESCALE project focusing on the design and initial implementation of the Dynamic Hardware Analyzer component of the RESCALE architecture. This component, as Task 3.3 indicates, provides side channel leakage assessment of some cryptography hardware or software Intellectual Property (IP) block. The designed and developed platform is adopting the latest research directives on Side Channel Attack (SCA) assessment and takes also into account remote SCAs on cloud based Field Programmable Gate Array (FPGA) units that accommodate multiple tenants. The deliverable initially provides an overview of the SotA on the SCA research domain and then analyzes the Dynamic Hardware Analyzer architecture and its components. Furthermore, in the deliverable we map open issues and future activities on hardware vulnerabilities and leakage detection that will be incorporated in the Dynamic Hardware Analyzer in the future (till the end of T3.3) and describe a brief road-map on the next activities to achieve this goal while in parallel also providing some initial results.