P‐10: MicroLED Pixel Circuit with A Novel NMOS‐Oxide TFT Inverter for Reducing Falling Time and Enhancing Gray‐Level Expression

In this paper, we propose a new circuit that significantly reduces the falling time by adopting a novel oxide thin‐film transistor (TFT)‐based inverter for pulse width modulation (PWM). Compared to existing n‐channel metal‐oxide‐semiconductor (NMOS)‐only pixel circuits that rely solely on the SWEEP signal, the falling time is significantly reduced to 0. 125 μs, enabling the expression of up to 25 gray levels without wavelength shift or pulse distortion.

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Publication Details

Journal
SID Symposium Digest of Technical Papers
Published
2025-06-01
DOI
https://doi.org/10.1002/sdtp.18459
Primary Topic
Geochemistry and Geologic Mapping
Type
article
Field-Weighted Citation Impact
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article

P‐10: MicroLED Pixel Circuit with A Novel NMOS‐Oxide TFT Inverter for Reducing Falling Time and Enhancing Gray‐Level Expression

SID Symposium Digest of Technical Papers
Geochemistry and Geologic Mapping
article

P‐10: MicroLED Pixel Circuit with A Novel NMOS‐Oxide TFT Inverter for Reducing Falling Time and Enhancing Gray‐Level Expression

article en

Abstract

In this paper, we propose a new circuit that significantly reduces the falling time by adopting a novel oxide thin‐film transistor (TFT)‐based inverter for pulse width modulation (PWM). Compared to existing n‐channel metal‐oxide‐semiconductor (NMOS)‐only pixel circuits that rely solely on the SWEEP signal, the falling time is significantly reduced to 0. 125 μs, enabling the expression of up to 25 gray levels without wavelength shift or pulse distortion.

SID Symposium Digest of Technical PapersVol. 56(1)
Seoul National University (KR)
Openalex Percentile: Top 70%
Geochemistry and Geologic Mapping
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P‐10: MicroLED Pixel Circuit with A Novel NMOS‐Oxide TFT Inverter for Reducing Falling Time and Enhancing Gray‐Level Expression · SID Symposium Digest of Technical Papers (2025) | TGRS Research Map | TGRS