99‐1: Design‐Technology Co‐Optimization of TFT Backplane for Ultrasound Pulse‐Echo Systems

This paper contains an analysis of an ultrasound pulse‐echo system with a TFT backplane, and considers how the trade‐off between resistance, capacitance and voltage tolerance can be navigated during technology development To this end, the link budget is calculated, the losses in the backplane are quantified, the optimal device width is calculated and a contour plot with the trade‐off between the performance and voltage tolerance is shown