Improved Dual-Capacitor CMOS Oscillator

This paper presents an improved fully integrated CMOS oscillator and compares it with a conventional topology, a version with current steering, and latest research. The oscillator is based on alternately charging two ground-referenced capacitors to limit transition times between periodic cycles. The topologies were compared in XFAB 350 nm technology node for a clock period of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.5~\mu $ </tex-math></inline-formula>s to ensure consistency. The proposed topology was also scaled down to 22 nm to demonstrate its excellent performance in modern nodes. In this paper, we describe a method for benchmarking the oscillator period for different segments. This enabled us to better understand the root cause of distortion and compensate for it. Our proposed topology uses fewer components than a common dual-capacitor topology while performing better and with fewer transitional distortions. The clock errors of the conventional topologies were −16 ns and +12 ns, whereas that of the proposed topology was only +4 ns. Finally, we discovered that the clock error is predominantly caused by the comparator, which encourages us to conduct further research on improving the comparator topology.