39‐1: <i>Invited Paper:</i> A Multi‐Drop High‐Speed Link with Foveated Up‐Scaler to Reduce Wires and Data Bandwidth in LED‐on‐Silicon‐Backplane for AR Glasses

This paper presents amulti‐drop high‐speed link of micro LED‐on‐Silicon (LEDoS) display with foveated upscaling for AR glasses. By utilizing multi‐drop connection of MIPI C‐PHY, number of wires between host processor and LEDoS display module could be reduced from 36 to 6 wires with 1 trio per each left and right eye for data transmission. In order to maximize sampling timing margin, self‐calibrated sampling phase is proposed regardless of jitter induced by multi‐drop channel. Additionally, foveated upscaling technique is proposed to reduce total data bandwidth, and as a result, a 1.5Gsps MIPI C‐PHY single trio can be used to transmit 3.5Gbps for AR glasses application. A silicon backplane is fabricated in a 28nm CMOS process and verified up to 2.0Gsps per trio in the MIPI C‐PHY on multi‐drop channel.

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Publication Details

Journal
SID Symposium Digest of Technical Papers
Published
2025-06-01
DOI
https://doi.org/10.1002/sdtp.18208
Primary Topic
Prenatal Screening and Diagnostics
Type
article
Field-Weighted Citation Impact
0.00
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article

39‐1: Invited Paper: A Multi‐Drop High‐Speed Link with Foveated Up‐Scaler to Reduce Wires and Data Bandwidth in LED‐on‐Silicon‐Backplane for AR Glasses

SID Symposium Digest of Technical Papers
Prenatal Screening and Diagnostics
article

39‐1: Invited Paper: A Multi‐Drop High‐Speed Link with Foveated Up‐Scaler to Reduce Wires and Data Bandwidth in LED‐on‐Silicon‐Backplane for AR Glasses

article en

Abstract

This paper presents amulti‐drop high‐speed link of micro LED‐on‐Silicon (LEDoS) display with foveated upscaling for AR glasses. By utilizing multi‐drop connection of MIPI C‐PHY, number of wires between host processor and LEDoS display module could be reduced from 36 to 6 wires with 1 trio per each left and right eye for data transmission. In order to maximize sampling timing margin, self‐calibrated sampling phase is proposed regardless of jitter induced by multi‐drop channel. Additionally, foveated upscaling technique is proposed to reduce total data bandwidth, and as a result, a 1.5Gsps MIPI C‐PHY single trio can be used to transmit 3.5Gbps for AR glasses application. A silicon backplane is fabricated in a 28nm CMOS process and verified up to 2.0Gsps per trio in the MIPI C‐PHY on multi‐drop channel.

SID Symposium Digest of Technical PapersVol. 56(1)
Samsung (South Korea) (KR)
Openalex Percentile: Top 33%
Prenatal Screening and Diagnostics
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