Design and Implementation of a Physically Secure Open-Source FPGA and Toolchain

The increasing prevalence of security breaches highlights the importanceof robust hardware security measures. Among these breaches, physical attacks– such as Side-Channel Analysis (SCA) and Fault Injection (FI) attacks – posea significant challenge for security-sensitive applications. To ensure robust systemsecurity throughout its lifecycle, hardware security updates are indispensable alongsidesoftware security patches. Programmable hardware plays a pivotal role in establishinga robust hardware root-of-trust, serving to effectively mitigate various hardwaresecurity threats. In this paper, we propose a methodology for the design of areconfigurable fabric and the corresponding mapping toolchain, specifically tailoredto hardware security. This approach offers resistance to various malicious physicalattacks, includingSCAandFI, addressing each threat individually. As a case study,we propose a resulting fabric that implements a combination of first-order BooleanMasking and hiding countermeasures to provide strong protection againstSCAattacksand enables the detection of fault injection attempts. In particular, we present howreconfigurable secure gadgets can be realized employing a reformed variant of theLUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) hardware maskingscheme and a modified version of Wave Dynamic Differential Logic (WDDL) tobe composed into a fabric. We also show how any basic Hardware DescriptionLanguage (HDL) design is automatically mapped to the primitives of our fabric,embedding provable hardware security, and bypassing the necessity for hardwaresecurity proficiency in this process. It is worth mentioning that our fabric requiresapproximately 85% less area to map a secure design compared to conventional FieldProgrammable Gate Arrays (FPGAs). A practical security evaluation of our securefabric implementation on a realFPGAtarget board, using Test Vector LeakageAssessment (TVLA), demonstrated no SCA leakage over 100 million traces.

Publication Details

Journal
KITopen
Published
2025-01-01
DOI
https://doi.org/10.5445/ir/1000184046
Primary Topic
Theoretical and Computational Physics
Type
article
Field-Weighted Citation Impact
0.00
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article

Design and Implementation of a Physically Secure Open-Source FPGA and Toolchain

KITopen
Theoretical and Computational Physics
article

Design and Implementation of a Physically Secure Open-Source FPGA and Toolchain

article en

Abstract

The increasing prevalence of security breaches highlights the importanceof robust hardware security measures. Among these breaches, physical attacks– such as Side-Channel Analysis (SCA) and Fault Injection (FI) attacks – posea significant challenge for security-sensitive applications. To ensure robust systemsecurity throughout its lifecycle, hardware security updates are indispensable alongsidesoftware security patches. Programmable hardware plays a pivotal role in establishinga robust hardware root-of-trust, serving to effectively mitigate various hardwaresecurity threats. In this paper, we propose a methodology for the design of areconfigurable fabric and the corresponding mapping toolchain, specifically tailoredto hardware security. This approach offers resistance to various malicious physicalattacks, includingSCAandFI, addressing each threat individually. As a case study,we propose a resulting fabric that implements a combination of first-order BooleanMasking and hiding countermeasures to provide strong protection againstSCAattacksand enables the detection of fault injection attempts. In particular, we present howreconfigurable secure gadgets can be realized employing a reformed variant of theLUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) hardware maskingscheme and a modified version of Wave Dynamic Differential Logic (WDDL) tobe composed into a fabric. We also show how any basic Hardware DescriptionLanguage (HDL) design is automatically mapped to the primitives of our fabric,embedding provable hardware security, and bypassing the necessity for hardwaresecurity proficiency in this process. It is worth mentioning that our fabric requiresapproximately 85% less area to map a secure design compared to conventional FieldProgrammable Gate Arrays (FPGAs). A practical security evaluation of our securefabric implementation on a realFPGAtarget board, using Test Vector LeakageAssessment (TVLA), demonstrated no SCA leakage over 100 million traces.

KITopen
Openalex Percentile: Top 46%
Theoretical and Computational Physics
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