HetSub: A Heterogeneous Multi-NoC With Reconfigurable Long-Range Links for Neuromorphic Systems

Network-on-chip (NoC) is widely employed in neuromorphic systems due to its excellent multicore communication performance. High energy consumption poses a critical challenge for NoCs, with static power becoming a major concern as technology nodes advance. This issue is even more pronounced in neuromorphic computing, which gains advantages from sparsity. However, current NoC architectures in neuromorphic hardware demonstrate limited optimization for static power consumption. While traditional multicore processor solutions that combine power gating (PG) and multiple NoC (Multi-NoC) can be applied to neuromorphic hardware, several limitations persist, such as serialization latency and low network utilization. In this article, we propose a lightweight heterogeneous Multi-NoC architecture that leverages the locality of neuromorphic computing to enhance network utilization, avoid serialization latency, and reduce power consumption. To address the issue of excessive communication distances for global packets in low traffic, we further propose a reconfigurable long-range link design and a heuristic long-range link insertion algorithm. By utilizing idle bandwidth resources in the PG subnetwork as a shortcut, we effectively improve latency. In addition, our design supports global reconfigurability to adapt to various application scenarios. The experimental results demonstrate that our proposed architecture outperforms the state-of-the-art Catnap, achieving a 16% saving in area, a 38% improvement in average packet latency, and a 58% reduction in static power consumption under real application workloads.