A 40-nm 26.4 mW, 18.6 MS/s Image Reconstruction Processor for IoT Compressive Sensing

Compressive sensing (CS) is a technique that compresses data using fewer samples, enabling efficient data transmission in Internet-of-Things (IoT) applications. However, reconstruction of compressively sensed data is computationally demanding, especially for 2-D images. This article presents the first image CS reconstruction processor for real-time visual streaming. The chip adopts a tailored iterative thresholding algorithm to ensure robust reconstructed image quality. Energy and area efficiencies are improved through algorithm-architecture optimizations. Projection reformulation is performed to reduce both computational complexity and memory usage. The utilization of computing units in the sparse and inverse transform engines is maximized through hardware sharing. The sparsity extractor improves hardware utilization of the thresholding core by identifying non-zero coefficients. The proposed noise estimation strategy eliminates the idle cycles, reducing memory size for the buffered data by 83%. A speculation scheme for thresholding effectively reduces hardware complexity by 74%. The memory controller is designed to support simultaneous data access with a 55% reduction in memory size. Fabricated in a 40-nm CMOS technology, the chip integrates 6.4 M logic gates in an area of 4.24 mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {^{2}}$</tex-math> </inline-formula>. Targeting real-time streaming at 60 frames/s for VGA images, the proposed processor dissipates 26.4 mW at a clock frequency of 48 MHz from a supply voltage of 0.73 V. The chip achieves over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2000{\times }$</tex-math> </inline-formula> higher throughput with six orders of magnitude energy efficiency improvement than a high-end CPU. Compared to prior works for 1-D compressively sensed physiological signals, this work achieves at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27.2{\times }$</tex-math> </inline-formula> higher energy efficiency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.6{\times }$</tex-math> </inline-formula> higher area efficiency.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2025-01-01
DOI
https://doi.org/10.1109/jssc.2025.3596162
Primary Topic
Diverse Scientific and Economic Studies
Type
article
Field-Weighted Citation Impact
0.00
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article

A 40-nm 26.4 mW, 18.6 MS/s Image Reconstruction Processor for IoT Compressive Sensing

IEEE Journal of Solid-State Circuits
Diverse Scientific and Economic Studies
article

A 40-nm 26.4 mW, 18.6 MS/s Image Reconstruction Processor for IoT Compressive Sensing

article en

Abstract

Compressive sensing (CS) is a technique that compresses data using fewer samples, enabling efficient data transmission in Internet-of-Things (IoT) applications. However, reconstruction of compressively sensed data is computationally demanding, especially for 2-D images. This article presents the first image CS reconstruction processor for real-time visual streaming. The chip adopts a tailored iterative thresholding algorithm to ensure robust reconstructed image quality. Energy and area efficiencies are improved through algorithm-architecture optimizations. Projection reformulation is performed to reduce both computational complexity and memory usage. The utilization of computing units in the sparse and inverse transform engines is maximized through hardware sharing. The sparsity extractor improves hardware utilization of the thresholding core by identifying non-zero coefficients. The proposed noise estimation strategy eliminates the idle cycles, reducing memory size for the buffered data by 83%. A speculation scheme for thresholding effectively reduces hardware complexity by 74%. The memory controller is designed to support simultaneous data access with a 55% reduction in memory size. Fabricated in a 40-nm CMOS technology, the chip integrates 6.4 M logic gates in an area of 4.24 mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {^{2}}$</tex-math> </inline-formula>. Targeting real-time streaming at 60 frames/s for VGA images, the proposed processor dissipates 26.4 mW at a clock frequency of 48 MHz from a supply voltage of 0.73 V. The chip achieves over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2000{\times }$</tex-math> </inline-formula> higher throughput with six orders of magnitude energy efficiency improvement than a high-end CPU. Compared to prior works for 1-D compressively sensed physiological signals, this work achieves at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27.2{\times }$</tex-math> </inline-formula> higher energy efficiency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.6{\times }$</tex-math> </inline-formula> higher area efficiency.

IEEE Journal of Solid-State Circuits
National Taiwan University (TW), Yonsei University (KR), The University of Texas at Austin (US), Tsinghua University (CN)
Openalex Percentile: Top 37%
Diverse Scientific and Economic Studies
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