ControlPULPlet: A Flexible Real-time Multicore RISC-V Controller for 2.5-D Systems-in-Package

The growing complexity of real-time (RT) control algorithms with increasing performance demands along with the shift to 2.5-D technology drive the need for scalable controllers to manage chiplets’ coupled operation in 2.5-D systems-in-package (SiPs). These controllers must offer RT computing capabilities, as well as SiP-compatible IO interfaces for communicating with the controlled dies. Due to RT constraints, a key challenge is minimizing the performance penalty of die-to-die (D2D) communication with respect to native on-chip control interfaces. We address this challenge with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ControlPULPlet</i>, an open-source, RT multicore RISC-V controller designed specifically for SiP integration. ControlPULPlet features a 32-bit CV32RT core for fast interrupt handling and a specialized direct memory access engine to automate periodic sensor readout. A tightly coupled programmable multicore cluster for acceleration of advanced control algorithms is integrated through a dedicated AXI4 port. A flexible AXI4-compatible D2D link enables efficient communication in 2.5-D SiPs. We implemented and fabricated ControlPULPlet as a silicon demonstrator called <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Kairos</i> in TSMC’s 65-nm CMOS. Kairos runs model predictive control algorithms at up to 290 MHz in a 30 mW power envelope. The D2D link attains a peak duplex transfer rate of 51 Gbit/s at 200 MHz, at the minimal costs of just <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {7.6~kGE }$ </tex-math></inline-formula> in PHY area per channel, adding just 2.9% to the total system area.