Utvärdering av prestanda för sidstorlekar av virtuellt minne och cache konfigurationer på Gitter Boltzmann-metoden

This thesis analyzes the impact of virtual memory page size and Translation Lookaside Buffer (TLB) configuration on performance with stencil-based computations, particularly with the memory intensive Lattice Boltzmann Method. Through the gem5 simulator, we analyzed the effect of page sizes (4 KiB and 64 KiB) on execution time, TLB size, and translation behavior. We benchmarked the accuracy of gem5’s simulations using hardware performance measurements from the HAICGU ARM-based HPC cluster. Our results demonstrate improved TLB hit rates with larger page sizes for sequential access patterns. The benefit for random access is limited when working sets exceed TLB coverage. Although gem5 was not able to simulate TLB behavior flawlessly, the simulator accurately captured the trends within TLB and cache behavior.