Stralingstolerante en Verouderingsresistente Digitale Geïntegreerde Schakelingen in Nanoscale CMOS Technologie.

Fault-tolerant integrated circuits are the central component of reliable systems that manage critical applications operating in harsh environments, including high-energy nuclear facilities, space missions, and medical instruments. Advanced CMOS integrated circuits endure reliability degradation regardless of the operating environment due to intrinsic aging degradation mechanisms. In addition, integrated circuits operating in harsh environments face exacerbated reliability challenges due to high radiation levels. This PhD project investigated the impact of the aging degradation mechanism on the radiation susceptibility of 28-nm UTBB FD-SOI technology node. In addition, it evaluated the efficiency of mitigation techniques in designing a fault-tolerant high-performance microprocessor without compromising long-term reliability. The research carried out for this work followed a quantitative approach. A test structure was designed in 28-nm UTBB FD-SOI technology node to assess the effect of the aging degradation mechanisms on the radiation susceptibility. The investigation included several accelerated irradiation test campaigns and in-depth analyses to gain a comprehensive understanding of the underlying mechanisms. The long-term radiation assessment for the 28-nm FD-SOI technology guided the design of a RISC-V fault-tolerant multicore microprocessor. This was a practical demonstration of how accurate radiation assessment helps design reliable SoCs. The total ionizing dose (TID) irradiation measurements and analyses for the pre-aged test structures revealed that the aging mechanism has a different impact on the radiation susceptibility depending on the device type. The heavy-ion irradiation tests and analyses illustrated that the increase of single event upset (SEU) cross-section for aged circuits is 2X higher at low LET, compared to the 1.4X increase in the cross section of SEU at high LET. This indicates that for low LET, any slight change in device characteristics due to aging degradation will significantly impact the sensitivity of SEU. The designed multicore fault-tolerant microprocessor demonstrated that implementing both avoidance strategy and detection and correction strategy is an efficient methodology, as this reduces the total overhead of the used fault-tolerance and mitigation techniques.