Sammankopplingslängduppskattning för avancerade CMOS-noder

Accurate wire length estimation is critical for early-stage physical design in advanced CMOS nodes. Traditional wire length estimation models, such as those proposed by Donath and Davis, have been widely used to predict interconnect distributions. However, their assumptions—such as uniform placement, rigid grid structures, and simplified interconnect probability functions—do not fully capture the complexities of modern physical designs. This thesis aims to refine these models by incorporating more realistic placement constraints and empirical validation. The first part of the study focuses on extracting Rent’s coefficients using two different methods: the Growing Box Method and the Recursive Splitting Method. Both methods yield nearly identical Rent exponents, differing only at the second decimal place, but the Recursive Splitting Method offers significantly reduced computation time. Next, the traditional wire length estimation models of Donath and Davis are evaluated. Donath’s model shows a significant deviation from actual distributions, likely due to its reliance on hierarchical placement, whereas the project focuses on PnR based placed designs. Davis’ model provides better accuracy for longer interconnects but fails to capture short-range interconnect behavior, leading to overestimations by orders of magnitude. To address these limitations, this thesis proposes a hybrid wire length estimation model. The Davis model is optimized by adjusting its power-law exponent to better fit empirical data for longer interconnects. However, short interconnect behavior is modeled separately using Monte Carlo simulations. This approach accounts for non-uniform cell sizes, pin locations, and realistic placement constraints. The final combined model achieves a strong fit to real design data, with an R2 value of 0.984. The study also identifies key challenges, including the sensitivity of wire length estimation to binning choices in PDFs. To mitigate this, CDFs are used instead, improving stability and accuracy. Additionally, the transition point between short and long interconnect models remains an area for potential refinement. Future work could focus on extending the model to purely a priori wire length estimation by starting from a circuit graph and integrating partitioning and placement techniques rather than relying on post-layout data. Further refinements could also involve improving transition continuity between short and long interconnect models, and generalizing the approach to heterogeneous integration scenarios.