Security assessment methodology for RISC-V cores

The rise in RISC-V processor adaptation in today’s electronic landscape is also bringing more security threats to them. In this context, we have developed a methodology to evaluate the security of RISC-V cores against side-channel attacks. The methodology is conceived to be compatible with any RISC-V core and it is focused on the analysis on power traces while the processor is running a cryptographic software algorithm on it. To validate the methodology, we extract power traces of the execution of an AES on a Rocket RISC-V core.