Design of High Efficiency Class E Power Amplifier Utilizing 0.18-µm RF CMOS Technology for 5G Network

The design of high-efficiency class E power amplifiers faces challenges due to low transistor breakdown voltages, high parasitic capacitances, and limited quality of on-chip passive components, which reduce power efficiency and linearity. Existing solutions offer moderate efficiencies but often require complex trade-offs that are not ideal for high-frequency applications. This research aims to optimize a class E power amplifier design to achieve higher efficiency and output power for 5G newtork, addressing these limitations while maintaining performance suitable for modern wireless communication systems. This paper proposed a high efficiency class E PA for 5G network. The proposed PA is implemented using the 0.18-µm RF CMOS process technology, and the circuit is designed and simulated using Cadence software. The proposed PA consists of a power stage and a driver stage. The power stage and the driver share a single source. The simulation results show that at input power of 0 dBm and supply voltage of 1.8 V, the proposed PA demonstrates a maximum peak power added efficiency (PAE) of 55 %. Meanwhile, a maximum output power (Pout) of 13.1 dBm is delivered by the proposed PA. Since the PA exhibits a stability factor (K value > 1), it is unconditionally stable. In addition, the PA achieves s-parameter of S11, S22 and S21 performances of -13.8 dB, -29.3 dB and 19.7dB, respectively. Furthermore, the layout of the proposed PA is 1.82 mm2 including the pads.