Development and Optimization of Electric-Double-Layer Gated Transistors Based on Low-Dimensional Materials: Gate-All-Around InAs Nanowire Arrays and Graphene Channels

Electric-double-layer (EDL) gating is a promising alternative to conventional gating methods for field-effect transistors (FETs), with potential applications spanning current logic, future logic, and neuromorphic computing architectures. This technique employs mobile ions in an electrically insulating but ionically conductive medium to generate strong local electric fields at the gate-to-channel interface, achieving field magnitudes on the order of 1 V/nm. These intense local fields enable significant charge carrier accumulation in the semiconducting channel, positioning EDL gating as a strong candidate for device applications. In this study, we investigate the use of low-dimensional channel materials, including two-dimensional graphene and one-dimensional InAs nanowires, in EDL-gated FETs. InAs nanowires, with electron mobilities approximately 30 times higher than silicon, offer a compelling alternative channel material for next generation electronic devices. For the first time, we report the development of an EDL gate-all-around (GAA) vertical InAs nanowire (NW) array geometry grown directly on a monolayer graphene film. This free-standing NWs geometry offers significant scaling potential and improved compatibility with current logic architectures. Initial characterization shows an on-state current of 16.5 μA/μm with an off-state current of 0.06 μA/μm, demonstrating comparable performance to existing lateral devices. Investigation reveals significant room for improvement by optimization of NW composition and processing conditions, with expected on-state current of 105 μA/μm with an off-state current of 30 pA/μm. 105 μA/μm. Additionally, we demonstrate the fabrication and optimization of FETs based on mechanically exfoliated two-dimensional materials within the RIT cleanroom. This process, initially demonstrated on graphene, is extensible to other 2D films such as transition metal dichalcogenides (TMDs), including exfoliated and epitaxially grown layers. These advancements pave the way for future exploration of neuromorphic and brain-inspired computing devices based on these material systems.

Publication Details

Journal
RIT Scholar Works (Rochester Institute of Technology)
Published
2024-12-01
Primary Topic
Laser Design and Applications
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article
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Development and Optimization of Electric-Double-Layer Gated Transistors Based on Low-Dimensional Materials: Gate-All-Around InAs Nanowire Arrays and Graphene Channels

RIT Scholar Works (Rochester Institute of Technology)
Laser Design and Applications
article

Development and Optimization of Electric-Double-Layer Gated Transistors Based on Low-Dimensional Materials: Gate-All-Around InAs Nanowire Arrays and Graphene Channels

article en

Abstract

Electric-double-layer (EDL) gating is a promising alternative to conventional gating methods for field-effect transistors (FETs), with potential applications spanning current logic, future logic, and neuromorphic computing architectures. This technique employs mobile ions in an electrically insulating but ionically conductive medium to generate strong local electric fields at the gate-to-channel interface, achieving field magnitudes on the order of 1 V/nm. These intense local fields enable significant charge carrier accumulation in the semiconducting channel, positioning EDL gating as a strong candidate for device applications. In this study, we investigate the use of low-dimensional channel materials, including two-dimensional graphene and one-dimensional InAs nanowires, in EDL-gated FETs. InAs nanowires, with electron mobilities approximately 30 times higher than silicon, offer a compelling alternative channel material for next generation electronic devices. For the first time, we report the development of an EDL gate-all-around (GAA) vertical InAs nanowire (NW) array geometry grown directly on a monolayer graphene film. This free-standing NWs geometry offers significant scaling potential and improved compatibility with current logic architectures. Initial characterization shows an on-state current of 16.5 μA/μm with an off-state current of 0.06 μA/μm, demonstrating comparable performance to existing lateral devices. Investigation reveals significant room for improvement by optimization of NW composition and processing conditions, with expected on-state current of 105 μA/μm with an off-state current of 30 pA/μm. 105 μA/μm. Additionally, we demonstrate the fabrication and optimization of FETs based on mechanically exfoliated two-dimensional materials within the RIT cleanroom. This process, initially demonstrated on graphene, is extensible to other 2D films such as transition metal dichalcogenides (TMDs), including exfoliated and epitaxially grown layers. These advancements pave the way for future exploration of neuromorphic and brain-inspired computing devices based on these material systems.

RIT Scholar Works (Rochester Institute of Technology)
Industry, innovation and infrastructure
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Laser Design and Applications
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Development and Optimization of Electric-Double-Layer Gated Transistors Based on Low-Dimensional Materials: Gate-All-Around InAs Nanowire Arrays and Graphene Channels · RIT Scholar Works (Rochester Institute of Technology) (2024) | TGRS Research Map | TGRS