Hardware Applications of High-Speed Fault Detection Algorithms

The growing need for a sustainable electric energy infrastructure has driven research into control, protection, and optimization of power systems. A key challenge is that the changing grid must operate at increasingly higher speeds, but many current hardware devices cannot meet these demands. This thesis focuses on power system protection, aiming to design a hardware solution that can detect and isolate faults in microseconds, ensuring faster, more reliable grid operations. The first hardware developed was for a low-voltage direct current (LVdc) microgrid, which faces challenges due to a lack of protection schemes and novel speed requirements. This thesis presents protection schemes implemented on a hardware device, with the necessary digital signal processing for sampling, filtering, and data storage. The hardware was tested in a Hardware-in-the-Loop (HIL) setup with a Real-Time Digital Simulator (RTDS), demonstrating fault location detection within only a few microseconds, outperforming commercial relays. The second protection algorithm implemented was a time-domain, source-agnostic distance relay for an ac transmission system, which has more complex topologies and fault types, requiring higher data processing capabilities. This paper reports on the performance of both hardware solutions, comparing the results from hardware and simulations. Finally, it discusses the potential of parallel computing in protection schemes and the limitations of high-speed digital signal processing on the microcontrollers used, especially in filtering, communication, and memory management.