FPGA Design of a Spiking Neural Network accelerator for optical event-based high-speed embedded digital cameras

Spiking Neural Networks (SNNs) are an interesting alternative to Artificial Neural Networks (ANNs) in applications such as event-based vision systems, given their compatibility in processing sparse events and achieving energy-efficient computation. FPGAs offer a valuable solution for SNN acceleration due to their reconfigurable logic, parallel processing, and low-power operation. However, implementing large-scale SNNs on FPGAs is challenging due to constraints in logic resources and memory. This work proposes a resource reutilization strategy to minimize logic utilization, reducing hardware complexity while maintaining computational accuracy. The SNN architecture is based on the Leaky Integrate-and-Fire (LIF) neuron model and is highly parameterizable, allowing for configurability in the number of neurons, weight precision and membrane potential width. Training and testing were conducted using snnTorch with the MNIST dataset to assess classification accuracy under varying configurations. The hardware implementation was validated on the Zynq UltraScale+ ZU5CG FPGA, achieving resource usage of 4137 LUTs and 4202 registers. The proposed architecture achieves an inference time of 0.09 ms and energy consumption of 0.04 mJ per inference, demonstrating its suitability for implementing hardware-efficient SNNs on FPGAs without substantial performance degradation.