UVM-Based Verification of a Configurable Data Flow-Control IP Core for FPGA CNN Accelerators

Artificial Intelligence (AI) and deep learning are reshaping data analysis, with Convolutional Neural Networks (CNNs) driving applications like image recognition and language processing. For real-time, AI at the edge, specialized hardware accelerators such as Field-Programmable Gate Arrays (FPGAs) are essential due to their flexibility and efficiency. Among FPGA-based solutions, FPG-AI, a framework from the University of Pisa’s EleSys Lab, enables streamlined CNN deployment on FPGAs by generating custom HDL code optimized for accuracy, speed, and resource usage. This thesis addresses the verification of FPG-AI’s scheduler block, a core component that coordinates timing and data flow. A Universal Verification Methodology (UVM)-based environment was developed in SystemVerilog to test scheduler functionality under varied conditions. The test campaign, based on a LeNet configuration with MNIST data, validated the scheduler’s stability and achieved intermediate code coverage. Future work could expand this verification through parametric sweep testing across additional configurations, network models, and datasets to explore edge cases and improve robustness, ensuring reliable performance across a broader set of applications.