Réseau de neurones artificiel sans multiplication avec calcul dans la mémoire en technologie 28nm CMOS FDSOI pour applications embarquées

Artificial intelligence (AI) techniques, and more specifically artificial neural networks (ANNs), are a major trend in the electronics industry, with applications ranging from connected devices to biomedical and industrial applications. As the complexity and classification performance of ANNs increase drastically, it has become essential to reduce their hardware integration costs, both in terms of power consumption and surface area, in order to facilitate their on-chip integration while guaranteeing optimum classification or detection performance.The vast majority of ANNs are based on computational models and multiplication and addition or accumulation (MAC) operations, and this thesis focuses on fully connected feed-forward networks (FNNs), which, along with convolutional networks (CNNs), are certainly the most common type of network. The most direct and effective way of reducing the cost of integrating ANNs is therefore to reduce the cost of these MAC operations. The reference metric for the energy efficiency of a computing system is the number of tera-operations per second per Watt (TOPS/W). If we consider a neuron, which can be thought of as a basic computing unit equivalent to a defined number of MACs, then in our context the hardware integration cost of the MACs is dominated by the cost of the feature weight products and therefore of the multiplication operations in particular. In this thesis, the ANN weights are quantized using a non-uniform logarithmic method, which in practice replaces the multiplication operation with a bit-shifting operation that requires much less silicon area and power consumption, with limited degradation in classification performance. In addition, this quantization approach enables data to be encoded on 4 bits with an equivalent resolution of 8 bits.Architecturally, the energy efficiency of the neuron is improved by the use of an unconventional architecture with in-memory computation (IMC). In a conventional implementation based on the von-Neumann (VN) architecture, it is necessary to constantly exchange data between a memory array and the computational elements. These memory exchanges have a cost and limit both energy efficiency and the computation or inference frequency of operation. IMC architecture, on the other hand, is based on a scheme in which there is no data movement between the memory and the computing elements. This mode of computation allows the IMC architecture to save energy and operating time for the same computation, the constraint being to integrate the processing elements in the memory array as close as possible to the memory cells (SRAM, DRAM, RRAM, etc.) without interfacing or with the most limited interface possible. In order to achieve multi-layer network inference on a limited surface and at a lower energy cost, an iterative approach is implemented: a single unique layer is physically implemented with each processing element linked to four different memory points, enabling up to four successive layers to be calculated in a loop on the same single layer via a system combining three-state logic and data concurrency on common lines.An FNN of maximum dimensions 32x32x32x32, i.e. 4 successive layers of 32 neurons, physically implemented in the form of a single iterative layer of 32 neurons, was designed in 28nm CMOS FDSOI technology and integrated on chip. A test layer of only 2 neurons was also implemented on-chip in order to study and measure the performance of a single neuron as well as the scaling effects for a larger network. The simulation results give an energy efficiency of the 32x32x32x32 network of 26.7 TOPS/W for single-layer inference and 22.8 TOPS/W for an inference on 4 successive layers. The operation of the network was validated using three different application cases: sleep apnea and cardiac arrhythmia, as well as image classification using the MNIST database in order to demonstrate the application flexibility and genericity of the solution.