Periphery design for fast-operation on multipillar VGSOT MRAM memories

This thesis investigates advancements in Voltage-Gated Spin-Orbit Torque (VGSOT) MRAM, building on previous research in MRAM technology. It focuses on optimizing both the read and write periphery design of VGSOT-4MTJ (four Magnetic Tunnel Junctions) memory bitcells for high-density, energy-efficient computing. The main objective is the design and simulation of optimized read and write circuits for a 2kB subarray, utilizing nanosheet transistors from a new process development kit (PDK). The VGSOT-4MTJ bitcell enhances bit density by 2.7x over traditional SRAM but introduces challenges in writability, selectivity, and power consumption due to the shared Spin-Orbit Torque (SOT) track across multiple MTJs. This thesis addresses these complexities by optimizing key parameters like the Spin Hall angle and Voltage-Controlled Magnetic Anisotropy (VCMA) coefficient for selective writing. Additionally, a precharged current mirroring sensing architecture is introduced, improving read speed and energy efficiency. The write periphery design focuses on minimizing the writing current to selected MTJs while preventing unintentional switching of neighboring MTJs, addressing critical challenges in writing selectivity.