Fundamentele en praktische aspecten van gateoxide-doorslag in VLSI-technologieën

Time-dependent dielectric breakdown is a reliability issue that has received a tremendous amount of attention in the past by many research groups. Also in imec, solid expertise exists on the modelling and statistics of TDDB. In the past decade, the problem disappeared from the academic radar - especially in FEOL - as it was not considered to be the most stringent reliability issue. The focus shifted to BEOL where intermetal dielectric thickness and line spacing reduced to the point that TDDB became a considerable problem. Typical BEOL TDDB concerns relate to dielectric quality and line edge roughness inducing local field-enhanced breakdown. In recent technologies, TDDB has, however, returned as a FEOL reliability concern. The gate stack in modern technologies is carefully tuned for optimal operation. Different metal gates are combined with a dielectric stack consisting of various high-k components. Dipole-inducing implants and defect annealing are used to optimize the work function while at the same time minimizing the impact of charge trapping causing bias-temperature instabilities (BTI). Although this meticulous optimization was beneficial for operation and some reliability issues, it also reduced the breakdown strength of the gate stack, bringing TDDB back as a reliability problem.