Modeling of ACF–COG Interconnection Resistance and Optimization of Process Parameters

The chip-on-glass process is a core technology in the production of liquid crystal displays, primarily utilizing thermosetting curing glue and various conductive particles within anisotropic conductive adhesive film to achieve interconnection. The resistance of the chip after interconnection serves as a crucial evaluation index for material selection and process parameters. This study aims to establish a simulation system for chip interconnect resistance and to explore the optimal process parameters for chip packaging with a consistent distribution of conductive particles. In this regard, numerous experiments are conducted to determine the bump interconnection resistance of the chip using CP6530ID anisotropic conductive adhesive film under various process parameters and the number of conductive particles captured by the bump, with the experimental data undergoing statistical analysis. Subsequently, the sequential thermal-mechanical coupling method is utilized to simulate the coupling method of binding temperature and pressure. After determining the deformation variables of conductive particles in CP6530ID anisotropic conductive adhesive film under a thermodynamic coupling field, the chip interconnection resistance is calculated using the established mathematical model of conductive particle interconnection resistance, and the interconnection resistance calculation results are compared with experimental results to verify the validity of the simulation results and the guiding significance of the experiment. The optimization starting point is based on the packaging process parameter range recommended by Sony Chemical. By randomizing the distribution of conductive particles, the study explored the optimal process parameters for chip packaging, using the simulation results as a reference. The findings indicate that under effective chip packaging conditions, the chip interconnect resistance is minimized at a binding temperature of 190 ℃ and a binding pressure of 100 MPa. During the chip packaging process, pressure is a decisive factor in the interconnection resistance, while the influence of temperature on the interconnection resistance is relatively weak. In terms of pressure factors, the greater the pressure, the smaller the interconnection resistance, without considering the fracturing of conductive particles. Conversely, higher temperatures lead to more intense thermal expansion of conductive particles, increasing the interconnection resistance.