High Performance Computing on RISC-V Architectures: Exploring Efficiency, Scalability, and Compiler Optimization for Modern Systems.

Computational performance and efficiency are increasingly critical in the design of High Performance Computing (HPC) systems, especially as demand grows for sustainable, high-performance computing solutions and necessitates a shift toward open and flexible architectures. Traditional HPC systems, dominated by x86 and ARM-based architectures, faces several challenges, high power con- sumption, and limitations in architectural adaptability. RISC-V, an open-source Instruction Set Architecture (ISA), presents a compelling alternative, offering cus- tomizability, energy efficiency, and extensibility for emerging HPC workloads. Through exploration of RISC-V based single board computers (SBCs), this thesis examines the feasibility of RISC-V in HPC environments, with a focus on performance optimization, compiler level tuning and software support to analyze their suitability for computationally intensive tasks. Additionally, the study also investigates parallelization strategies, utilizing OpenMP and OpenMPI, to en- hance performance, benchmarked results provide empirical evidence of RISC-V’s computational efficiency, comparing its performance against x86 and ARM-based systems. This research highlights RISC-V’s potential to revolutionize HPC by de- livering scalable, energy-efficient, and customizable computing solutions by using quantitative and qualitative insights. By offering insights into efficient, scalable computing, this research con- tributes to the ongoing development of more adaptable HPC solutions tailored to emerging workloads and technologies. It demonstrates the pathway forward for integrating RISC-V architecture in HPC systems, showcasing its potential to rev- olutionize performance while enhancing sustainability and flexibility in real-time, resource-intensive applications. Keywords: HPC, Single Board Computers (SBC), Performance, RISCV, ISA