Efficient FPGA based Implementation of a 64-bit Parallel Prefix Adder

Binary addition forms the backbone of computational arithmetic, serving as a core operation in Digital Signal Processing, arithmetic and logic units, microprocessors, and microcontrollers. As adders are integral to these applications, ongoing research aims to optimize their performance. The propagation of the carry bit significantly affects an adder's delay, making its design critical. In this paper, we propose and evaluate an efficient design for a 64-bit parallel prefix adder (PPA), a high-speed adder that balances performance with resource utilization. Unlike ripple carry adders (RCA), which suffer from serial delay issues, and carry look-ahead adders (CLA), which mitigate delay at the cost of increased complexity, PPAs leverage prefix operations for fast and efficient addition. Our proposed PPA achieves a critical path delay of 23.21 ns, demonstrating high-speed performance with low power consumption and reduced area overhead. The design was developed using Verilog HDL, simulated, and synthesized using the Xilinx ISE tool. These results highlight the PPA's suitability for VLSI designs, offering an optimal trade-off between speed, area, and power for modern computational systems.