Design och optimering av en Reed-Solomon avkodare med Högnivåsyntes

Forward Error Correction (FEC) is an error correction coding technique in which redundant information is added to transmitted data to enable bit error correction at the receiver. Reed-Solomon(RS) coding is a FEC scheme based on Galois field arithmetic which is popular in applications requiring low bit error rates and high communication speeds, such as serial communication links between logic devices and analog-digital converters. As these communication links progress in performance, there is increased demand for area-effective RS-FEC architectures that support high-frequencies. High Level Synthesis (HLS) is a digital design methodology in which Register Transfer Level (RTL) descriptions are generated from models implemented in high-level programming languages such as SystemC, a set of libraries for C++. This methodology aims to reduce development times and allow for easier design space exploration. This thesis aims to use the HLS methodology to compare a number of RS-FEC architectures, with a view to finding architectures that are well suited to high-frequency operation. In this work a decoder architecture based on the Berlekamp-Massey algorithm is implemented in SystemC before being optimised and translated into an RTL model using Siemens Catapult HLS. Architectural optimisations such as improved Galois field multiplication architectures and the reformulated Inversionless Berlekamp Massey (riBM) algorithm are also implemented in SystemC and the generated RTL models are compared. Finally, logic synthesis is then carried out on each design using Synopsys Design Compiler. The maximum achievable frequency and area of the synthesised decoders are then compared to each other. The results indicate the traditional Berlekamp-Massey decoder has the highest maximum acheivable frequency of the decoders considered, but has twice the area compared to the flawed riBM-based implementations. Additionally, the HLS methodology is found to be a viable but limited methodology, and its merits and drawbacks are discussed.

Publication Details

Journal
KTH Publication Database DiVA (KTH Royal Institute of Technology)
Published
2025-01-01
Primary Topic
Coding theory and cryptography
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article
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article

Design och optimering av en Reed-Solomon avkodare med Högnivåsyntes

KTH Publication Database DiVA (KTH Royal Institute of Technology)
Coding theory and cryptography
article

Design och optimering av en Reed-Solomon avkodare med Högnivåsyntes

article en

Abstract

Forward Error Correction (FEC) is an error correction coding technique in which redundant information is added to transmitted data to enable bit error correction at the receiver. Reed-Solomon(RS) coding is a FEC scheme based on Galois field arithmetic which is popular in applications requiring low bit error rates and high communication speeds, such as serial communication links between logic devices and analog-digital converters. As these communication links progress in performance, there is increased demand for area-effective RS-FEC architectures that support high-frequencies. High Level Synthesis (HLS) is a digital design methodology in which Register Transfer Level (RTL) descriptions are generated from models implemented in high-level programming languages such as SystemC, a set of libraries for C++. This methodology aims to reduce development times and allow for easier design space exploration. This thesis aims to use the HLS methodology to compare a number of RS-FEC architectures, with a view to finding architectures that are well suited to high-frequency operation. In this work a decoder architecture based on the Berlekamp-Massey algorithm is implemented in SystemC before being optimised and translated into an RTL model using Siemens Catapult HLS. Architectural optimisations such as improved Galois field multiplication architectures and the reformulated Inversionless Berlekamp Massey (riBM) algorithm are also implemented in SystemC and the generated RTL models are compared. Finally, logic synthesis is then carried out on each design using Synopsys Design Compiler. The maximum achievable frequency and area of the synthesised decoders are then compared to each other. The results indicate the traditional Berlekamp-Massey decoder has the highest maximum acheivable frequency of the decoders considered, but has twice the area compared to the flawed riBM-based implementations. Additionally, the HLS methodology is found to be a viable but limited methodology, and its merits and drawbacks are discussed.

KTH Publication Database DiVA (KTH Royal Institute of Technology)
Industry, innovation and infrastructure
Openalex Percentile: Top 72%
Coding theory and cryptography
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