Design of Miniaturized On-chip Monopole Planar Antenna with loaded Interdigital Capacitor for 5.8 GHz Devices

Miniaturization of the on-chip antenna (OCA) in the lower frequency band is limited by the requirement for a compact chip size imposed by the larger electrical wavelength. At the same time, shrinking the antenna size reduces radiation characteristics and incurs significant losses due to lossy silicon substrate. This paper introduces a design for a miniaturized monopole planar on-chip antenna utilizing an interdigital capacitor (IDC) as an approach. The design incorporates a partially reflective surface (PRS), characterized by a high impedance surface, into the stacked structure to enhance antenna performance at a resonant frequency of 5.8 GHz. The stacked-up structure comprises a six-layer metal-insulator-semiconductor (MIS) integrated onto a monolithic silicon substrate as the host material. A model prototype was fabricated using a sputtering process, resulting in a size reduction of 45.62 % compared to conventional designs, well-suitaed for the applications of RFIC, Wi-Fi, WiMAx, RFIC, and wireless transceivers at 802.11a. The fabricated antenna is validated and realizes an improved gain of 28.63 % and a radiation efficiency of 25.26 %, with an impedance bandwidth of 0.73 GHz at a return loss of about 20 dB.