Event-gedreven circuit architecturen voor schaalbare en adaptieve sensor uitlezing

The continuous monitoring of vital body signs such as the electrocardiogram (ECG) and electroencephalogram (EEG) signals is crucial for the early detection of health issues. Achieving long-term monitoring with wireless connectivity, however, poses significant challenges. Sensing devices for vital signals must operate for extended periods of time on small, portable batteries, making an ultra-low energy consumption a critical concern. Often, on-chip data reduction through digital signal processing is necessary to meet the energy budget constraints. While digital signal processing can extend the battery life, innovative sensor architectures are needed for even larger power savings. This doctoral research addresses the need for energy-efficient sensing devices by focusing on event-driven processing in the mixed-signal domain. By investigating event-driven sensing techniques that adaptively adjust the sampling rate based on the signal activity of time-sparse signals such as the ECG or action potentials (AP), the research aims to minimize the power consumption of the sensing device as well as the transmission power. This will be explored in the thesis by investigating event-driven level-crossing ADCs (LCADCs). First, the advantages of LCADCs are thoroughly investigated. The circuit limitations of LCADCs are analyzed by means of a behavioral MATLAB model. Next, an analytical model for the LCADC power consumption is derived. Two comparisons are performed between the LCADC architecture and a conventional Nyquist-rate ADC with digital compression: one at the ADC level and one at the system level. At the ADC level, LCADC power models are compared with power models of a SAR ADC, the most commonly used ADC architecture in conventional biomedical systems. The aim is to determine the conditions under which LCADCs are more power efficient. At the system level, LCADCs are compared with SAR ADCs with digital compression to assess the system-level benefits of the LCADC topology. LCADCs prove to be more power-efficient compared to SAR ADCs for low to medium resolutions (e.g., up to 6.8 bits for ECG and EEG in a 40nm CMOS technology). Conventional LCADCs are limited by the fixed power consumption of the continuous-time (CT) comparator and, if applicable, the time-to-digital converter (TDC). At system level, LCADCs that directly stream the data off-chip can significantly reduce the data transmission power, up to two orders of magnitude for a 5-bit resolution, and achieve an order of magnitude power reduction for an 8-bit resolution. However, for applications where the LCADC output needs to be retimed with a TDC, no significant advantage over digital compression is observed. Hence, the research focuses on improved LCADC architectures. The first IC design presented addresses the limitations of conventional LCADCs by introducing an LCADC with discrete-time (DT) comparators and adaptive clocking. By using DT comparators instead of CT comparators, a significant power consumption reduction can be achieved. To exploit the time-sparse properties of the signals, an adaptive-clocking strategy is employed, where the ADC sampling rate is adjusted using an on-chip clock generator and off-chip event logic on an FPGA. This adaptive-clocking strategy can enable a 10-100× power saving in the comparator. A prototype chip is fabricated in a 40nm CMOS technology, with an 8-bit quantizer resolution and 15-kHz bandwidth. The fabricated LCADC exhibits a variable power consumption, ranging from 0.92 µW for an ECG input to 5.38 µW for a full-scale 15-kHz sine input. The design achieves an effective number of bits (ENOB) of 10.4 bits, a best-case Walden signal-to-noise-and-distortion ratio (SNDR)/dynamic range (DR) figure of merit (FoM) of 138/119.8 fJ/conversion step, and a best-case Schreier SNDR/DR FoM of 158.85/152 dB. The system-level benefits of this topology are demonstrated through a 30% data reduction for ECG applications. To build upon the first prototype, a second IC is presented, the FREYA SoC. This IC extends the synchronous LCADC to a multi-channel analog-to-spike converter (ASC), which generates spiking inputs for an on-chip spiking neural network (SNN) processor. The FREYA prototype chip consists of an 8-channel, time-division-multiplexed ASC and an integrated SNN processor. Thanks to the adaptive system clock and the multiplexing, the proposed ASC can reuse the same hardware for each channel. The ASC also features a programmable adaptive-resolution algorithm, allowing the tuning of the spike encoding to any signal of interest. A custom training framework for the SoC can efficiently and rapidly tune the ASC and SNN towards a specific application, reducing the required training epochs of the SNN by 69% compared to a full grid search. The framework has been demonstrated for the QRS-labeling task based on ECG, achieving a maximum accuracy of 98.67%. A prototype IC fabricated in a 40nm CMOS technology demonstrates significant improvements in chip area efficiency, with a per-channel active area of only 0.023 mm2/channel (0.184 mm2 in total), a 7-fold improvement over similar works. For the QRS-labeling task, the system consumes 20.8 µW/channel and 13.29 µJ/classification, with an SNN clock running at 15 MHz (VDD at 0.56V), and achieves a latency of 80 ms. The two presented prototype ICs significantly improve upon the previous limitations of LCADCs and extend the functionality of these data converters, paving the way for signal-scalable, low-power event-driven SoCs for biomedical sensing devices.