Fast Prioriterad Dynamisk Schemaläggning av 3-fas Uppgifter på RP2040 : Ett ramverk för att undvika minneskonflikter

The advent of multi-core platforms offers new possibilities for embedded system design, but also introduces complexities in memory hierarchies that complicate timing analysis. To improve predictability in task execution, a separation between memory access and computation phases is essential. By separating shared memory access to distinct phases and ensuring that computation relies solely on local memory, interference between tasks during execution can be minimized. This approach enhances system reliability, particularly in real-time applications where timing precision is critical. This thesis introduces a 3-phase task execution framework tailored for the RP2040 multi-core platform to alleviate memory contention and ensure consistent application development. The framework leverages a custom linker script to achieve memory bank privatization, hardware spin locks for managing memory region access, and timer interrupts for task scheduling. Six application benchmarks, adapted from the TACLeBench suite, serve as evaluation metrics. Tasks are dynamically scheduled based on fixed priorities, it is then verified that contention has been eliminated completely. A comparative analysis is conducted between this framework, employing a dynamic online scheduler with local function definitions, and an alternative implementation using a static offline scheduler with global function defini- tions. The findings underscore the suitability of the thesis framework for applications prioritizing time-critical operations over memory constraints.