UVM BASED VERIFICATION OF EE621 RISC PROCESSOR MODULE

In the process of digital design, the majority of efforts are focused on verification. This is because a proper verification environment can help engineers discover bugs that otherwise would have flown under the radar. On the other hand, a poorly designed verification environment could fail to fully confirm the device’s functionality and leave the customer with a buggy mess. For obvious reasons, this should be avoided at all costs, hence the emphasis on functional verification and validation efforts. Throughout time, the complexity of the average design under test (DUT) has increased dramatically, making verification a significant challenge for today’s verification engineers. As such, the verification industry is always looking for more efficient methodologies. One such methodology is called the Universal Verification Methodology (UVM), which is a class library written in the SystemVerilog language. This paper discusses the framework of a self-checking testbench with contained random stimulus generation, created with the powerful tools of UVM, to verify the functionality of a Reduced Instruction Set Computer (RISC) Processor. The RISC processor was written with Verilog HDL and was the final project of the EE621: Design of Computer Systems class at RIT. The testbench was run for both RTL and Netlist simulations using Cadence Xcelium. It was found that the DUT would pass the self-checking testbench for approximately 90% of runs. Functional coverage metrics that outline the testbench’s effectiveness were extracted and reported. From these metrics, it was proven that the UVM testbench was able to generate random instructions that covered 100% of the possible opcode, source register, and destination register values.