Network-on-Chip Packet Obfuscation and Encoding for Hardware Trojan Mitigation

Networks-on-Chip (NoCs) represent a transformative advancement in System-on- Chip (SoC) communication architectures, addressing the scalability and performance limitations of traditional bus-based systems. The increasing reliance on NoCs in modern SoCs has raised security concerns, particularly in untrusted fabrication environments. This thesis investigates the vulnerabilities posed by malicious hardware Trojans and untrusted IP cores, such as reverse engineering, misdirection attacks, and brute-force decryption. To counter these threats, the study introduces a robust security framework leveraging encoding and obfuscation techniques. Hamming codes are employed to detect and correct errors, ensuring data integrity and correcting misdirection attacks. Discrepancies between codewords and data words trigger tampered packet detection and prevent their propagation through the NoC. Obfuscation techniques, driven by dynamic keys generated by linear feedback shift registers (LFSRs), secure routing tables and packet headers. These dynamically updated keys ensure unpredictable routing paths, preventing route and router Trojan attacks and complicating reverse engineering. The proposed solutions are implemented in a 4x5 NoC architecture, with Verilog-based testbeds validating their effectiveness. Results demonstrate the system’s ability to detect and correct single- and double-bit errors, prevent packet injection, and counter misdirection attacks. The dynamic LFSR-based obfuscation ensures secure communication throughout NoC operation.

Publication Details

Journal
RIT Scholar Works (Rochester Institute of Technology)
Published
2025-04-01
Primary Topic
Prenatal Screening and Diagnostics
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article
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article

Network-on-Chip Packet Obfuscation and Encoding for Hardware Trojan Mitigation

RIT Scholar Works (Rochester Institute of Technology)
Prenatal Screening and Diagnostics
article

Network-on-Chip Packet Obfuscation and Encoding for Hardware Trojan Mitigation

article en

Abstract

Networks-on-Chip (NoCs) represent a transformative advancement in System-on- Chip (SoC) communication architectures, addressing the scalability and performance limitations of traditional bus-based systems. The increasing reliance on NoCs in modern SoCs has raised security concerns, particularly in untrusted fabrication environments. This thesis investigates the vulnerabilities posed by malicious hardware Trojans and untrusted IP cores, such as reverse engineering, misdirection attacks, and brute-force decryption. To counter these threats, the study introduces a robust security framework leveraging encoding and obfuscation techniques. Hamming codes are employed to detect and correct errors, ensuring data integrity and correcting misdirection attacks. Discrepancies between codewords and data words trigger tampered packet detection and prevent their propagation through the NoC. Obfuscation techniques, driven by dynamic keys generated by linear feedback shift registers (LFSRs), secure routing tables and packet headers. These dynamically updated keys ensure unpredictable routing paths, preventing route and router Trojan attacks and complicating reverse engineering. The proposed solutions are implemented in a 4x5 NoC architecture, with Verilog-based testbeds validating their effectiveness. Results demonstrate the system’s ability to detect and correct single- and double-bit errors, prevent packet injection, and counter misdirection attacks. The dynamic LFSR-based obfuscation ensures secure communication throughout NoC operation.

RIT Scholar Works (Rochester Institute of Technology)
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Prenatal Screening and Diagnostics
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Network-on-Chip Packet Obfuscation and Encoding for Hardware Trojan Mitigation · RIT Scholar Works (Rochester Institute of Technology) (2025) | TGRS Research Map | TGRS