Investigating the Performance Variation for Graphene-Based Field-Effect Transistor

As silicon CMOS technology approaches its scaling limits, two-dimensional (2D) materials such as graphene offer promising alternatives due to its atomically thin material property and high carrier mobility. Graphene field-effect transistors (GFETs) are especially suited for high-frequency and RF applications; however, large-scale integration is hindered by substantial device-to-device variability. Primary contributors include inconsistent graphene transfer, contact resistance, poor dielectric interfaces, and underlying substrate topography. This work presents a comparative study of three GFET architectures to address variability: (a) raised Al gate with 15 nm Al2O3, (b) raised Al gate with monolayer hexagonal boron nitride (hBN), and (c) recessed Al gate with monolayer hBN. By replacing Al2O3 with atomically flat hBN (~0.45 nm) and introducing a chemical-mechanical planarized (CMP) recessed gate, we significantly improved both performance and uniformity across 750+ fabricated devices. Results show the average Dirac voltage shifts from ~7.8 V (Al2O3/raised Al gate) to 1.2 V (hBN/raised Al gate) and further to 0.7 V (hBN/recessed Al gate). Contact resistance drops from 2.59 kΩ∙µm to 0.67 kΩ∙µm, and hole mobility variability reduces from 75% to 18%. Raman spectroscopy and SEM analysis confirm smoother surfaces and improved graphene integrity in the recessed gate structure. Mobility performance remained comparable across various structures, but the recessed gate configuration exhibited tighter distribution and greater reproducibility. Overall yield increased from 14.8% for the Al2O3/raised gate devices to 65.1% for the hBN/recessed gate structured devices. Heatmaps of yield, mobility, and Dirac voltage distribution illustrate that the planarized gate and improved dielectric interface led to spatially uniform and statistically consistent device behavior. Presented work highlights the importance of gate dielectric selection and geometry in minimizing GFET variability. The integration of monolayer hBN with a recessed gate provides a reproducible and scalable fabrication platform, reducing the impact of surface roughness and interface defects. This work evaluates complete device distributions, revealing statistically significant improvements in performance and reliability. Our results establish a practical pathway for wafer-scale GFET integration using hBN dielectrics and planarized gate structures for advancing two-dimensional based transistors toward high-yield, high performance electronics.