Thermal resistance research of power devices based on structural function curve correction method

This study investigated the thermal resistance of various layers within power devices. To this end, thermal resistance tests were conducted on an IGBT module, leading to the plotting of its structural function curve. This module was then structurally modeled, and subsequent transient thermal simulations produced another structural function curve that was converted from the temperature rise curve. A fitting process was introduced to correct the measurement curve. The structural function distribution of thermal resistance in the interface materials at various layers was obtained from the corrected structural model. The corrected thermal resistance values were 0.510, 4.085, 4.085, 20.430 ,7.149, 5.106, and 26.550 K/kW for the chip layer, chip solder layer, DBC copper layer (upper), alumina ceramic layer, DBC copper layer (lower), substrate solder layer, and substrate, respectively. Furthermore, power cycling and passive thermal cycling tests were performed to verify the degenerate interval of thermal resistance before and after these tests, indicating substantial agreement between the test data and theoretical results.

Publication Details

Journal
SHILAP Revista de lepidopterología
Published
2025-03-01
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
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article

Thermal resistance research of power devices based on structural function curve correction method

SHILAP Revista de lepidopterología
Silicon Carbide Semiconductor Technologies
article

Thermal resistance research of power devices based on structural function curve correction method

article en

Abstract

This study investigated the thermal resistance of various layers within power devices. To this end, thermal resistance tests were conducted on an IGBT module, leading to the plotting of its structural function curve. This module was then structurally modeled, and subsequent transient thermal simulations produced another structural function curve that was converted from the temperature rise curve. A fitting process was introduced to correct the measurement curve. The structural function distribution of thermal resistance in the interface materials at various layers was obtained from the corrected structural model. The corrected thermal resistance values were 0.510, 4.085, 4.085, 20.430 ,7.149, 5.106, and 26.550 K/kW for the chip layer, chip solder layer, DBC copper layer (upper), alumina ceramic layer, DBC copper layer (lower), substrate solder layer, and substrate, respectively. Furthermore, power cycling and passive thermal cycling tests were performed to verify the degenerate interval of thermal resistance before and after these tests, indicating substantial agreement between the test data and theoretical results.

SHILAP Revista de lepidopterología
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Silicon Carbide Semiconductor Technologies
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