A Dual-Core RISC-V Processor with a Two-Level Programmable Cache Emulation and Test System

The Compiler Lease of Cache Memory (CLAM) project has previously explored the effects of lease-based replacement policies for benchmarks (programs) run on single-core with single-level and single-core with two-level cache architectural config- urations. This work builds and expands on this prior work by continuing the same line of inquiry for a dual-core with two-level cache architectural configuration. The lease-based replacement policies studied are: Compiler Assigned Reference Leasing (CARL), Phased Reference Leasing (PRL), Scope Hooked Eviction Leasing (SHEL), and Cross-Scope Hooked Eviction Leasing (C-SHEL). These are compared to the per- formance of the traditional Pseudo Least Recently Used (PLRU) replacement policy. Samples are collected from PolyBenchC benchmark runs using PLRU on a single- core with two-level cache configuration. These are then used to generate leases for the dual-core with two-level cache configuration. On the latter, the benchmarks run in pairs and in multi-tasking mode, i.e., one on each core with private L1 instruction and data caches, but with shared L2 cache and main memory. The number of misses seen