A High-Efficiency LDO Regulator with Adaptive PSRR and Transient Enhancements

Reliable power delivery is essential for all computing systems, particularly those operating with limited or constrained energy sources, such as batteries. Power management circuits must provide energy efficiency, stability, and resilience to disturbances to support accurate and consistent system performance. This thesis presents a high-efficiency low-dropout (LDO) regulator featuring adaptive power supply rejection ratio (PSRR) and transient response enhancement techniques. By leveraging adaptive analog design strategies, the proposed regulator dynamically boosts performance at high load currents, maintaining optimal efficiency across the full load range while circumventing key trade-offs inherent to conventional LDO architectures. The design incorporates several novel circuit techniques to improve overall performance relative to state-of-the-art solutions. Implemented in a 55 nm CMOS process, the regulator is validated through extensive simulation, layout, and silicon fabrication, with physical testing to follow upon chip delivery. Its utility is further demonstrated through integration in a time-domain neuromorphic system, highlighting its applicability in edge computing environments.