Fault tolerant Operations in Majorana-based Quantum Codes: Gates, Measurements and High Rate Constructions

Majorana-based quantum computation in nanowires and neutral atoms has gained prominence as a promising platform to encode qubits and protect them against noise. In order to run computations reliably on such devices, a fully fault-tolerant scheme is needed for state preparation, gates, and measurements. However, current fault-tolerant schemes have either been limited to specific code families or have not been developed fully. In this work, we develop a general framework for fault-tolerant computation with logical degrees encoded into Majorana hardware. We emphasize the division between even and odd Majorana codes and how it manifests when constructing fault tolerant gadgets for these families. We provide transversal constructions and supplement them with measurements to obtain several examples of fault tolerant Clifford gadgets. For the case of odd codes, we give a novel construction for gadgets using quantum reference frames, that allows to implement operations that are forbidden due to parity superselection. We also provide a fault-tolerant measurement scheme for Majorana codes inspired by Steane error correction, enabling state preparation, measurement of logical operations and error correction. We also point out a construction for odd Majorana codes with transversal T gates. Finally, we construct a high rate quantum LDPC Majorana code with logical qubits. Our work shows that all necessary elements of fault-tolerant quantum computation can be consistently implemented in fermionic hardware such as Majorana nanowires and fermionic neutral atoms.