Speedup Chip Yield Analysis by Improved Quantum Bayesian Inference

The semiconductor chip manufacturing process is complex and lengthy, and potential errors arise at every stage. Each wafer contains numerous chips, and wafer bin maps can be generated after chip testing. By analyzing the defect patterns on these wafer bin maps, the steps in the manufacturing process where errors occurred can be inferred. In this letter, we propose an improved quantum Bayesian inference to accelerate the identification of error patterns on wafer bin maps, thereby assisting in chip yield analysis. We outline the algorithm for error identification and detail the implementation of improved quantum Bayesian inference. Our results demonstrate the speed advantage of quantum computation over classical algorithms with a real-world problem, highlighting the practical significance of quantum computation.