High-Speed Energy-Efficient Signed Multiplier For FPGA Based Hardware Accelerators

Abstract:In modern digital system architectures, multiplication is essential for performing computational tasks such as convolution operations, which are extensively utilized in applications related to digital signal processing (DSP). These operations require signed multipliers that are both high-speed and energy-efficient to fulfill the requirements of performance-critical applications. Multiplication is inherently resource-intensive and has a considerable effect on speed and performance of processors, making the design of fast and efficient multiplication units essential. This work focuses on designing multiplier that operates at a high-speed and consumes less power. The implementation and design of the multipliers with lesser delay and power supports rapid prototyping and customization, making them ideal for FPGA based real-time processing applications.