Optimized Advanced Encryption Standard Using Verilog HDL

Abstract: Cryptography plays a crucial role in ensuring the confidentiality, integrity, and protection of sensitive information during both transmission and storage. Earlier encryption schemes like DES were widely adopted but gradually became less effective due to limitations such as fixed key lengths and vulnerability to modern cryptanalytic techniques. To overcome these issues, the Advanced Encryption Standard (AES) was developed, offering enhanced security by supporting variable key sizes of 128, 192, or 256 bits and operating on 16-byte data blocks.Initially intended for high-security systems, AES has since been broadly utilized in safeguarding large volumes of private data across networks and embedded platforms. This project focuses on a power-efficient and lightweight AES-based image encryption system implemented using Verilog HDL. Verilog is chosen over VHDL due to its lower latency and faster synthesis, making it more suitable for real-time applications.To enhance power efficiency, clock gating is incorporated into the design. This technique reduces power consumption by disabling the clock signal to inactive modules, thus lowering dynamic power usage without compromising performance. The proposed approach delivers a high-speed and energy-efficient encryption mechanism tailored for applications with limited power resources, such as portable healthcare devices, IoT systems, and secure multimedia communications