POWER EFFICIENT 16-T HYBRID FULL ADDER FOR PORTABLE APPLICATIONS

The Full Adder (FA) circuit designed with different methodologies forming a hybrid logic configuration is proposed. The foremost oddity of these hybrid methodology based full adder is to effectively utilize the advantageous feature of different logic style incorporated in a single design. Such a power optimized 1-bit hybrid FA cell is proposed with pass transistor logic, transmission gate logic and gate diffusion input technique. The hybrid combination results in reduction of total transistor count without performance degradation, due to the usage of different logic style at required positions. The proposed FA circuit is implemented using 16-transistors to achieve optimum performance. The proposed circuit is designed using DSCH2 and simulated in Microwind tool by using various CMOS technology. Comparison of the design metrics for the proposed 1-bit hybrid FA cell against the existing FA circuits is also carried out. The evaluation result shows that present study reported 71.9% power reduction in an average when applied to 90nm, 65nm and 45nm CMOS technologies. Furthermore, the FA circuit is verified for higher order bit length extending up to 128-bits which is suitable in various arithmetic applications.