Design and Implementation of Area and Power Efficient Elliptic Curve Cryptography Using Clock Gating

Abstract: With the power to provide high security and due to its lower consumption of resources, ECC today stands as the best choice from the cryptographic point of view. ECC is defined as lightweight and thus suited for use cases with tiny computational resources: embedded platforms, IoT devices. This study centers around the design and development of an area-optimized ECC architecture, specifically tailored for implementation on FPGA-based systems. The primary goal is to minimize hardware footprint while maintaining high performance and ensuring strong cryptographic security. A major part of this effort involves refining and optimizing finite field arithmetic operations—namely, modular addition, multiplication, and inversion—which serve as the foundation for ECC computations. The design will integrate efficient point multiplication strategies such as the Montgomery ladder and various windowing techniques to boost operational speed and security resilience. We are going to mold the proposed software using language like Verilog or VHDL, which involves schematically designing of software and synthesizing or emulating the ultimate software user on Vivado by Xilinx, targeting specific FPGA boards for validation and performance evaluation.