GARD SIS Junction Fabrication ProcGARD SIS Junction Fabrication Process to serve Next Generation Receivers for ALMAess to serve Next Generation Receivers for ALMA

ALMA Development Roadmap sets the goal of ``increase of the receiver IF bandwidth by at least a factor of two'' to address the three new fundamental science drivers: the origin of galaxies, the origins of chemical complexity and the origin of planets. From the SIS mixer device perspective, the goal of increasing the IF bandwidth by at least a factor of two translates into requirement to decrease of and keep tight control over the SIS junction capacitance, which is responsible for IF response roll off at higher frequencies. In turn, that calls for (1) the SIS junctions with a smaller area and, hence, capacitance, and (2) the material system for the SIS junctions tunnel barrier having a lower specific capacitance. Supported by ESO and in collaboration with NAOJ and NOVA, GARD was running the studies addressing both goals. As the outcome of the studies, GARD currently supports the process for fabricating of SIS junctions with AlN tunnel barrier and the junction area down to 1 sq.um or a bit below. The GARD SIS design rule supports the junctions with RnA>5 Ohm/sq.um along with the specific capacitance Cs(RnA) specification. The SIS junction quality characterized by the ratio of subgap to normal resistances, Rj/Rn>20 (often better). At the workshop, we will present the details about the GARD SIS fabrication process and design rule, as well as the available results of measurements of SIS mixer demonstrators utilizing the SIS junctions made with the upgraded GARD fabrication process.