Modeling of Digital Delays in Multi-Input Gates and Applications

This thesis focuses on models for accurate dynamic timing analysis in modern digital circuit design, particularly in the context of asynchronous circuits. In sharp contrast to analog simulations, which are very accurate but slow, digital dynamic timing analysis focuses on continuous-time signals with discrete (typically binary) value domains. Its main ingredient is accurate delay models for elementary gates like inverters, NAND and NOR, which allow tracking individual signal transitions throughout a circuit. Inspired by the simple thresholded hybrid model that was introduced as a by-product of the Involution Delay Model for single-input single-output gates like inverters some time ago, the focus of this thesis is to explore the suitability of such models for multi-input gates like NOR and NAND, where unique phenomena like delay variations induced by varying transition separation time on different inputs occur. In a nutshell, the thesis aims at analytic gate delay models that are accurate yet simple enough to (1) facilitate the derivation of analytic delay formulas for circuits made up of such gates and (2) simulate circuits faster than possible via expensive analog simulations.