Interface using fast USB for characterization of SPADs

Optical receivers, specifically avalanche photodiodes (APDs) and single-photon avalanche diodes (SPADs), are essential for various applications in optical communications and sensing technologies. Given the variability in their performance due to process parameters and environmental factors, efficient characterization methods are desirable.Commonly, characterization methods rely on high-speed oscilloscopes. These can be expensive and slow down the process due to data transfer limitations.To improve efficiency, this work proposes a cost-effective USB interface for streaming digital data from such optical receivers to a PC. Utilizing the CYUSB3KIT-003 EZ-USB FX3 SuperSpeed explorer kit for USB connectivity, the interface was developed with a topology of SPAD ⇒ comparator/level shifter ⇒ serial-to-parallel conversion⇒ FX3 ⇒ PC. Custom four-layer printed circuit boards (PCBs) were designed for each stage of the interface, including configuration for the comparator and level shifter stage, as well as two distinct serial-to-parallel conversion topologies: one based on daisy-chained shift registers and the other on cascaded demultiplexers/deserializers. Firmware for the FX3 was developed to facilitate data transfer, complemented by a simple Windows application for managing data transfers.Performance evaluations showed that the interface could operate effectively at continuous speeds up to 3050 Mbit/s, nearing the theoretical maximum of 3200 Mbit/sof the FX3 for USB connections. However, performance varied significatly across differet modules, with data integrity issues at certain speeds or conditions depending on the used topology.A discrete component strategy was chosen over an FPGA-based approach for the serial-to-parallel conversion stage due to its perceived advantages in chip availability, ease of troubleshooting and design time; however, this decision led to significant challenges and unsatisfactory performance results. Nevertheless, it led to a more cost-effective solution, avoiding the high recurring costs associated with FPGA design software licenses.While the developed interface is functional, its usability is hindered by data integrity concerns, necessitating further optimizations or alternative design strategies. Future work is recommended to explore FPGA-based solutions, leveraging insights gained from this thesis to enhance performance and flexibiliy while addressing the identified issues.