Enhancing single-instruction multiple-threads FPGA-based processors with high-bandwidth-memory

The gap between memory bandwidth and processing power has been expanding continuously. Not long ago, some memory technology initiatives have been proposed in order to bridge this disparity. One of the most promising solutions comes in the form of 3D stacked memories like High-Bandwidth Memory (HBM). By adding several and wider memory channels that can do memory transactions in parallel, these memories increase significantly the data throughput and aim to close the aforementioned gap. A popular way to prototype and test these memories is to integrate them with Field Programmable Gate Arrays (FPGAs) due to their high reconfigurability. Graphic Processing Units (GPUs) are another inherently parallel targeted hardware, and so some advances in integrating GPUs with HBM are already present in the industry. This new technology integration brings a paradigm shift because in order to fully take advantage of the parallel nature of HBM, the hardware design has to also support this highly parallel data throughput. While GPUs provide high data processing parallelism, FPGAs are known for their flexibility. Intellectual Property (IP) blocks are an example of this flexibility, because they are a bundle of Hardware Description Language (HDL) code which can be included in an existing implementation of an FPGA, adding functionality to it. Soft-IP-cores implemented on reconfigurable hardware, are a solution that offers advantages from both worlds, where a soft-GPU could be hosted in an FPGA. There is, however, a gap in knowledge on how 3D stacked memories support soft-GPU-cores. This thesis analyses this gap and provides insights into how HBM memories can be exploited in soft-GPU-cores. To accomplish such an endeavor, this thesis presents, evaluates, and analyzes a complete open-source environment that consists of a soft-GPU with HBM compatibility. The contributions are composed of several different tools ranging from the model simulator, to easy-to-use implementation flow on real hardware. The environment also includes a roofline model which is used to analyze how applications from different domains behave and can be optimized in the custom hardware.