Design and Implementation of a MIPI CSI-2 compatible receiver and pre-processor for low-resolution image processing

In this thesis, a MIPI CSI-2 compatible receiver for use with the GateMate FPGA by Cologne Chip AG was designed using the Verilog hardware description language and tested. Additionally, a demonstrator system, capable of pre-processing and forwarding the received data to a display via DVI, was developed to facilitate the design and testing of the receiver. This demonstrator system includes a dedicated evaluation board for the GateMate FPGA that was designed and assembled as a part of this work. A camera module that uses a CSI-2 interface for transmitting video data was used as a real data source to verify the function of the receiver and demonstrator. The key challenge was the handling of the D-PHY physical layer used by the CSI-2 interface with generic input buffers. To achieve this, some of the specified functionality of CSI-2 and the D-PHY physical layer, which is not necessary for video data reception, was omitted from the designed receiver, resulting in a compact design that does not require workarounds like doubling the number of I/O pins used for each “lane” of the interface. The results of initial tests show that the receiver manages to reliably receive video data from the camera module over several hours without any significant errors occurring. However, no in-depth characterization of the system’s performance could be done within the timeframe of this project.