Analog Computer Simulation with Automatic Scaling By Digital Computer

A computer-aided design approach for the simplification of analog computer simulation is presented. The simulation configuration consists of an EAI 2000 analog computer with serial communications link to a PDP — 11/24 digital computer. Under control of the PDP-11, the analog simulations are realized with appropriate time and magnitude scaling which adjusts the range of the simulation coefficients and prevents overloads of the analog components. The analog computer hardware configuration accommodates both stable plants up to eighth order and closed-loop systems up to tenth order. Cascade compensation is provided for the closed-loop systems. The plant may be described by either a transfer function, pole-zero locations, or a sum of first and second order sections. When given either of the first two descriptions, the PDP-11 software performs a partial fraction expansion. The plant is modeled in a modified diagonal or Jordan canonical form. Scaling of the simulation is presented. Magnitude scaling of the simulation variables is based on the unit step response of the first and second order sections of the plant model. Time scaling is used to adjust the range of the coefficients used to realize the simulation on the analog computer.

Institutions

Publication Details

Journal
ODU Digital Commons (Old Dominion University)
Published
2024-08-15
DOI
https://doi.org/10.25777/crw9-nz11
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Analog Computer Simulation with Automatic Scaling By Digital Computer

ODU Digital Commons (Old Dominion University)
VLSI and FPGA Design Techniques
article

Analog Computer Simulation with Automatic Scaling By Digital Computer

article en

Abstract

A computer-aided design approach for the simplification of analog computer simulation is presented. The simulation configuration consists of an EAI 2000 analog computer with serial communications link to a PDP — 11/24 digital computer. Under control of the PDP-11, the analog simulations are realized with appropriate time and magnitude scaling which adjusts the range of the simulation coefficients and prevents overloads of the analog components. The analog computer hardware configuration accommodates both stable plants up to eighth order and closed-loop systems up to tenth order. Cascade compensation is provided for the closed-loop systems. The plant may be described by either a transfer function, pole-zero locations, or a sum of first and second order sections. When given either of the first two descriptions, the PDP-11 software performs a partial fraction expansion. The plant is modeled in a modified diagonal or Jordan canonical form. Scaling of the simulation is presented. Magnitude scaling of the simulation variables is based on the unit step response of the first and second order sections of the plant model. Time scaling is used to adjust the range of the coefficients used to realize the simulation on the analog computer.

ODU Digital Commons (Old Dominion University)
Dominion University College (GH), Old Dominion University (US)
Openalex Percentile: Top 65%
VLSI and FPGA Design Techniques
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.