Design of an Event-based Zero-Crossing ADC for Interfacing Analog Frontend and SNN Accelerator

This Master thesis explores the design and implementation of a Zero-Crossing Analog-to-Digital Converter (ZCADC) tailored for neuromorphic front-ends. Neuromorphic hardware, inspired by the brain’s event-driven processing, offers power-efficient solutions for running spiking neural networks (SNNs). A key challenge in this domain is converting analog signals into spike-based representations compatible with these systems. The ZCADC architecture proposed in this work addresses this challenge by producing both spike outputs and digital words from analog inputs with a bandwidth range of 20Hz to 22kHz. The thesis evaluates various ZCADC design strategies, discussing their trade-offs and justifying specific design choices. It also details the building, testing, and verification phases of the circuit, ensuring that theoretical performance aligns with practical results. This research highlights a scalable, power-saving approach to audio signal conversion, with the flexibility to meet bandwidth and dynamic range requirements. It relaxes the strict offset constraints of the comparator by using a pre-amplifier and offers a modified way of generating outputs in the form of digital words. Moreover, the system has the capability of reaching ENoB of up to 11 bits. The current implementation achieved ENoB in the range of 4-6 bits with the power consumption spanning from 16-50 µW depending on the input signal activity. While the system demonstrates the potential efficiency, further research is required to optimize power consumption and refine the design for improved performance.