CNTFET-based SRAM cell Designing and Analysis by using Verilog-A code

This study introduces an innovative method for developing energy-efficient and high-speed Static Random Access Memory (SRAM) cells using Carbon Nanotube Field Effect Transistors (CNTFET). By replacing traditional Silicon dioxide with Silicon Nitride and Hafnium Di-Oxide in the substrate and gate dielectric, the proposed SRAM cells exhibit significant improvements in power consumption, delay, drain current, and noise margin compared to conventional MOSFET-based and standard CNTFET-based SRAM cells. This research explores various SRAM configurations, including standard and enhanced CNTFET-based designs, and presents a Reduced Power with Enhanced Speed (RPES) technique. Using simulations with the Stanford CNTFET model at 45nm technology node in Cadence Virtuoso, study demonstrates an improvement in power-delay product (PDP) for 6T SRAM cell over traditional designs. Impact of high-k dielectric on performance of enhanced CNTFET-based SRAM cells is investigated, providing recommendations for optimal configurations to achieve better stability and reduced leakage current.