Dynamically Reconfigurable Logic Array Partitioning for Accelerated Graph Neural Network Inference on FPGA-Based Cloud Accelerators

**Abstract:** This paper introduces a novel hardware acceleration strategy for Graph Neural Networks (GNNs) leveraging dynamically reconfigurable logic arrays (DRLAs) within FPGA-based cloud accelerators. Traditional GNN inference on FPGAs often suffers from static resource allocation, hindering efficiency across diverse graph architectures and layer configurations. Our approach, Dynamic Partitioning for Graph Acceleration (DPGA), employs a reinforcement learning (RL) agent to dynamically partition the DRLA into specialized processing units tailored to the specific computational demands of each GNN layer, achieving up to a 3.5x speedup and 20% reduction in power consumption compared to static partitioning methods. This method is immediately commercializable for cloud providers serving increasingly diverse GNN workloads. --- *This document is a part of the Freederia Research Archive. Explore our complete collection of advanced research at [en.freederia.com](https://en.freederia.com), or visit our main portal at [freederia.com](https://freederia.com) to learn more about our mission and other initiatives.*