Design of Single-Architecture Universal Shift Register and Counter with Memory Unit using Full-Swing GDI D-Flip-Flops

This research presents a novel single-architecture universal shift register/counter with an integrated memory unit. A full swing gate diffusion input (GDI) flip-flop is designed and implemented in both a synchronous counter and a universal shift register. SRAMs are mostly utilized as cache memory due to their ability to retain data when the power is ON. Hence, a 4 × 4 SRAM-based on full swing gate diffusion input flip-flop is developed to act as a memory for the proposed single-architecture universal shift register / Counter with the memory unit. To enhance performance, a 4 × 4 SRAM based on the proposed GDI flip-flop is incorporated as the memory unit. The design aims to improve key performance metrics, including clock-to-Q delay, power-delay product, area, and static power consumption. Simulation results demonstrate a 25% reduction in clock-to-Q delay, 30% reduction in D-to-Q delay, 20.2% reduction in power-delay product, 14.9% reduction in area, and 28.6% reduction in static power consumption compared to conventional D-flip-flop designs. The proposed architecture is validated through simulations using Tanner EDA at 1.2 V operating conditions, confirming its efficiency and potential applicability in high-performance sequential circuits.